Delete verilator.log

synthesizer/frequency_select/verilator.log

-TOP.testbench.cg with cycle_time_p          10
-
- _____         _   _               _      _____                                       _____     _         _   
-|_   _|___ ___| |_| |_ ___ ___ ___| |_   |   __|___ ___ ___ _ _ ___ ___ ___ _ _      |   __|___| |___ ___| |_ 
-  | | | -_|_ -|  _| . | -_|   |  _|   |  |   __|  _| -_| . | | | -_|   |  _| | |     |__   | -_| | -_|  _|  _|
-  |_| |___|___|_| |___|___|_|_|___|_|_|  |__|  |_| |___|_  |___|___|_|_|___|_  |_____|_____|___|_|___|___|_|  
-                                                         |_|               |___|_____|                        
-
-Begin Simulation:
-At Posedge           0: kypd_i = 0000000000000000, dut_freq_o = 000000000000000000000000, test_freq_o = 000000000000000000000000
-At Posedge           1: kypd_i = 0000000000000001, dut_freq_o = 000000000000000000000000, test_freq_o = 000000000000000100000110
-At Posedge           2: kypd_i = 0000000000000010, dut_freq_o = 000000000000000100000110, test_freq_o = 000000000000000100010101
-At Posedge           3: kypd_i = 0000000000000100, dut_freq_o = 000000000000000100010101, test_freq_o = 000000000000000100100110
-At Posedge           4: kypd_i = 0000000000001000, dut_freq_o = 000000000000000100100110, test_freq_o = 000000000000000100110111
-At Posedge           5: kypd_i = 0000000000010000, dut_freq_o = 000000000000000100110111, test_freq_o = 000000000000000101001010
-At Posedge           6: kypd_i = 0000000000100000, dut_freq_o = 000000000000000101001010, test_freq_o = 000000000000000101011101
-At Posedge           7: kypd_i = 0000000001000000, dut_freq_o = 000000000000000101011101, test_freq_o = 000000000000000101110010
-At Posedge           8: kypd_i = 0000000010000000, dut_freq_o = 000000000000000101110010, test_freq_o = 000000000000000110001000
-At Posedge           9: kypd_i = 0000000100000000, dut_freq_o = 000000000000000110001000, test_freq_o = 000000000000000110011111
-At Posedge          10: kypd_i = 0000001000000000, dut_freq_o = 000000000000000110011111, test_freq_o = 000000000000000110111000
-At Posedge          11: kypd_i = 0000010000000000, dut_freq_o = 000000000000000110111000, test_freq_o = 000000000000000111010010
-At Posedge          12: kypd_i = 0000100000000000, dut_freq_o = 000000000000000111010010, test_freq_o = 000000000000000111101110
-At Posedge          13: kypd_i = 0001000000000000, dut_freq_o = 000000000000000111101110, test_freq_o = 000000000000001000001011
-At Posedge          14: kypd_i = 0010000000000000, dut_freq_o = 000000000000001000001011, test_freq_o = 000000000000001000101010
-At Posedge          15: kypd_i = 0100000000000000, dut_freq_o = 000000000000001000101010, test_freq_o = 000000000000001001001011
-At Posedge          16: kypd_i = 1000000000000000, dut_freq_o = 000000000000001001001011, test_freq_o = 000000000000001001101110
-- testbench.sv:78: Verilog $finish
-Simulation time is               220000
-                   __ 
- _____            |  |
-|  _  |___ ___ ___|  |
-|   __| .'|_ -|_ -|__|
-|__|  |__,|___|___|__|
-
-Simulation Succeeded!